1. Field of the Invention
The present invention is in the field of digital electronics, and, in particular, is in the field of digital data communications. More particularly, the present invention is related to interface circuits wherein an asynchronous input signal is synchronized to a local clock signal.
2. Description of the Related Art
In the field of digital electronics, it is often necessary to pass control and data signals between first and second digital circuits operating under control of independent time bases (i.e., independent clock signals). The communication between the first and second digital circuits is referred to as asynchronous communication since the signals generated by the first circuit at a particular time with respect to its internal clock signal can be received by the second circuit at random times with respect to the internal clock signal of the second circuit. In other words, the two circuits are not synchronized with respect to each other.
In order for a signal from the first circuit to be utilized by the second circuit, it is necessary to synchronize the signal with the internal time base of the second circuit. It is well known in the field of digital electronics to include synchronization circuits as part of the interface circuits between two mutually asynchronous digital circuits. Such synchronization circuits typically include a flip-flop, or other such clocked data storage device, that is clocked by a synchronizing clock signal that is synchronous with the internal time base of the circuit receiving the input signal. In such circuits, the input signal, or a buffered signal responsive to the input signal, is clocked into the flip-flop when the signal level of the synchronizing clock signal makes a transition from a first signal level to a second signal level (i.e., a high-to-low transition or a low-to-high transition). After a short delay, referred to as the propagation delay through the flip-flop, a signal or signals responsive to the input signal will appear on one or more outputs of the flip-flop. The output or outputs of the flip-flop will thus be synchronized with the internal time base of the receiving circuit.
Although such flip-flop type synchronizing circuits generally operate satisfactorily, there are known conditions wherein the asynchronous input signal does not satisfy the setup and hold times of the flip-flop. That is the input signal arrives at the receiving circuit at a time such that the input signal is changing at approximately the same time as the synchronizing clock signal is making the transition that clocks the input signal into the flip-flop. If the input signal changes logic levels shortly before the clocking transition, it does not satisfy the required setup time for the flip-flop. If the input signal changes logic levels during or shortly after the clocking transition, it does not satisfy the required hold time for the flip-flop. When either of these events occur, it is possible for the flip-flop to respond to the input signal in an undesirable manner. Rather than the outputs of the flip-flop simply changing to respond to the change in the input signal or staying the same until the next clocking transition of the synchronizing clock, the outputs may oscillate for an amount of time (referred to as the settling time) before stabilizing in one of the two stable output conditions. This instability is caused by an inherent race condition in the flip-flop that occurs when the setup and hold times are not satisfied. Because of the asynchronous relationship between the time bases of the two circuits, the race condition cannot be prevented in a single flip-flop.
Various circuits have been developed to compensate for the race condition so that the instability of the synchronizing flip-flop is not allowed to affect the operation of the receiving circuit. One well-known method of synchronization is to double buffer the input signal by connecting first and second flip-flops in series such that the data output of the first flip-flop is connected to the data input of the second flip-flop. In such circuits, the second flip-flop is clocked at a sufficiently long time after the first flip-flop is clocked so that the output of the first flip-flop will have stabilized prior to the clocking of the second flip-flop. Since the two flip-flops are synchronized to the same internal time base, the setup and hold times for the second flip-flop can be guaranteed so that the output of the second flip-flop will be stable after the propagation delay through the second flip-flop. The output of the second flip-flop is provided as the synchronized input signal to the rest of the receiving circuit.
The foregoing improvement is adequate in many cases; however, at higher clock rates, such as are found in many commercially available digital circuits, the internal time base of the receiving circuit may have a periodicity that is less than the settling time of the first flip-flop. Thus, if the first and second flip-flop were to be clocked by a synchronizing signal operating at the frequency of the internal time base, there is an unacceptable probability that the second flip-flop will be presented with a signal from the first flip-flop that is oscillating. The state of the output of the second flip-flop after it is clocked will be unpredictable because the state of the input is unpredictable. In addition, the input to the second flip-flop may not satisfy the setup and hold times of the second flip-flop, thus causing the output of the second flip-flop to oscillate, a clearly undesirable condition.
The latter described problem can be solved in part by using a synchronizing clock derived from the internal time base that has a lower frequency than the internal time base. However, in many cases it is undesirable to use such a lower frequency synchronizing clock signal. One disadvantage to such a solution is that the lower frequency clock signal is typically generated from the internal time base by a flip-flop or other divider circuit and thus the transitions in the lower frequency clock signal are delayed with respect to the transitions in the internal time base. When the internal time base has a high frequency, such as 40-66 MHz in microcomputers based upon 20-33 MHz 80386 microprocessors, or the like, the additional propagation delay is a substantial portion of the period of the internal time base. Thus, it is not desirable to synchronize the received input signal with a lower frequency synchronizing signal when the remainder of the receiving circuit is clocked with the internal time base.
It can thus be seen that it is desirable to have a synchronization circuit that synchronizes a received asynchronous input signal with a high frequency internal time base clock while avoiding the race condition described above.